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Patent Details

Applicant:
Indian Institute of Technology (IIT) Roorkee 
Title:
A method of fabricating dual dielectric constant (Dual-k) spacers is source/drain region of a MOSFET 
Inventor(s):
S.K.Manhas, Anand Bulusu, and Saurabh Kumar Nema 
Applicant:
Indian Institute of Technology (IIT) Roorkee 
Application type:
Applied - 2012-10-10 
Application Number:
3164/Del/2012 
Applied at:
India 
Entered by:
Indian Institute of Technology (IIT) Roorkee 
Abstract:
The present invention is provided with a method of fabrication of dual/asymmetric dielectric constant spacers in multigate mosfet devices comprising the steps of removing SOI (Silicon on Insulator) wafers thin film by means of photo resist lithography; removing the silicon layer by means of dry etching thereby producing fin layer; depositing a thin oxide layer as dielectric on the fin portion in two stages; depositing Gate metal layer, nitride layer followed by chemical mechanical polishing; generating a protracted elevated portion at the centre by means of photo resist lithcgraphy; anisotropic dry etching for selective areas of the wafer substrates; depositing first spacer insulator film; photo resist lithography for spacer I dry etch; dry etching step of spacer- 1 and depositing spacer II insulator layer, undergoing process of chemical mechanical polishing (CMP), to be reformed into a solid uniform parallelopiped structure; photo resist lithography for Spacer II etch; spacer-Il dry etch; formation of dopinq region such as source drain (S/D) region on the spacer II layer followed by Ion implantation; Pre metal dielectric deposition thereby undergoing chemical mechanical polishing (CMP); removing insulating material by means of photolithography forming contact holes, thereby resulting in the formation of metal lines. The use of dual/asymmetric dielectric constant device/circuit with increased speed and reduced standby power dissipation.  

 
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