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Applicant:
Indian Institute of Technology (IIT) Gandhinagar 
Title:
A LATERAL DMOS TRANSISTOR AND METHOD OF FABRICATING THEREOF 
Inventor(s):
MANDAR SURESH BHOIR , NIHAR RANJAN MOHAPATRA 
Applicant:
Indian Institute of Technology (IIT) Gandhinagar 
Application type:
Applied - 2019-04-13 
Application Number:
201921014956 
Applied at:
India 
Entered by:
Indian Institute of Technology (IIT) Gandhinagar 
Abstract:
The present disclosure relates to the field of power semiconductor devices and envisages a Source side underlap LDMOS (SU LDMOS) transistor and a method of fabricating SU LDMOS. The SU LDMOS transistor includes a Source-, a Drain- and a Gate region. The fabrication method comprises the steps of Shallow-Trench Isolation (STI), Well implantation, Silicon dioxide (SiO 2 ) growth, poly-Silicon deposition and patterning (Gate-stack formation), drift region implantation, Spacer formation, S/D Implantation and Salicidation followed by Back-end of Line (BEOL). The method forms an underlap region between the Source and Gate regions, that introduces a resistance (R x ) at the Source end. The underlap region facilitates elimination of quasi-saturation and impact-ionization issues and improvement in on- state breakdown voltage (BV DS,on ) of said transistor, safe operating area, transistor’s output conductance (g ds ), intrinsic gain (g m /g ds ), and cut-off frequency (f T ). 

 
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