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  Digital Catalogue for Technology and Products Development


   Technology and Product Development

    Basic Information

Technology developed: An Efficient Software Transactional Memory Library for Multi-core Systems (TP19765260255)
Category: Product (Hardware/Material/Software)
Details of Inventor(s):
Inventor Institution/Organization/Company Department Designation
Dr. Sathya Peri IIT Hyderabad Computer Science & Engineering Associate Professor
Technical Application Area: Information Technology
If 'Other', please specify:
Please give more details of new technical application area:
Organization(s):
Indian Institute of Technology (IIT) Hyderabad
Affiliated Ministry: DRDO, Govt of India
Type of technology development: Collaboration with Foreign Entity
Does the technology help in replacing any import items currently
procured from outside India?
No
Does the technology have export potential? Yes
Category of Technology developed: Immediate Deployment
Stage of Development: Field Test
Please describe in detail including the TRL Level:
TRL1

    Abstract:

Applications: It can be used with any computational hardware that has multiple cores
Advantages: Around 2004, 50 years of exponential improvement in the performance of sequential computers ended. Although, the quantity of transistors on a chip continues to follow Moore'ss law (doubling roughly every two years), it has become increasingly difficult to continue to improve the performance of sequential processors. Instead of increasing the clock speed of processors, more cores are being put on a single chip. This parallel architecture offers a potential solution to the problem of stalled performance growth. The number of processors that can be fabricated on a chip will continue to increase as per the Moore’s law, at least for the next few generations. So, to exploit the parallel architecture, applications need to be parallel programmed, obviously for performance reasons. Unfortunately, parallel programming is far more difficult to design, maintain and debug than sequential programming. Formulating algorithms and proving their correctness is even more difficult. The bugs are non-deterministic and parallel programs often give poor performance. Adding to the woes, reasoning about parallel programs doesn’t come naturally to human mind. Keeping in mind the difficulties associated with traditional synchronization mechanism in parallel programming, alternatives constructs are needed, which removes the burden of all concurrency issues from programmer. Software Transactional Memory (STM) is one such construct. It takes care of all the synchronization difficulties. This product is such a library developed based on such a STM system. It is based on single-version and multi-version timestamp protocols which have been proved to be quite efficient.

    Technology Inputs:

Imported Equipment/Spare Parts:
Equipment/Spare Parts Year ITC-HS Code
NA
Indigenous Equipment/Spare Parts:
Equipment/Spare Parts Year ITC-HS Code
NA
Imported Raw Materials:
Raw Materials Year ITC-HS Code
NA
Indigenous Raw Materials:
Raw Materials Year ITC-HS Code
NA
Existing R&D Facilities used:
Facilities Year ITC-HS Code
NA

   Patents & Publications:

Patents:
Filed Patents (No.) Granted Patents (No.) Year
0 0 NA
Publications:
Submitted (No.) Published (No.) Year
0 1 2016-17

    Commercialization Potential:

Who are the Potential Licensees?
What commercially available products address
the same problem?
Company Product Problem Addressed
Would you like to develop this invention further with
corporate research support?
Yes
Would you be interested in participating in cluster based
programs for commercialization research or business
planning for your invention?
Yes
      Submitted by: The Dean R and D Date of Submission: 7-8-2020



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