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Applicant:
Indian Institute of Information Technology (IIIT) Pune 
Author:
Sandeep Mishra 
Corresponding Authors:
T. V. Mahendra, S. W. Hussain, A. Dandapat 
DOI #:
10.1109/TCSI.2020.2978295 
Title:
Energy-efficient precharge-free ternary content addressable memory (TCAM) for high search rate applications 
Journal:
IEEE Transactions on Circuits and Systems I: Regular Papers 
Year:
2020 
Volume:
67 
Page:
2345 - 2357 
Keywords:
Content addressable memory (CAM) , high search speed , low-power , precharge-free ternary CAM (PF-TCAM) 
Abstract:
Hardware search engines (HSEs) have been drawing significant attention in replacing software search algorithms in order to speed up location access and data association in modern systems. Content addressable memory (CAM) is one of the promising HSEs due to its parallel search accessibility. However, it is subjected to considerable dissipation which becomes severe while accessing many components including cells and associated matchlines (MLs) during every search. Ternary CAM (TCAM) based routing tables, especially employed in network systems for packet classification, has put a challenge to design energy-efficient architectures with high-performance and reliable look-up operation. Precharge-free CAM schemes are preferred solutions over precharge types to accomplish high-speed as well as low-power goals of associative memory design. In order to overcome the drawbacks of precharge based designs and also to improve performance during the search, we introduce a precharge-free ternary content addressable memory (PF-TCAM). The proposed searching approach enhances the rate of search by reducing half of the ML evaluation time as it eliminates precharge phase prior to every search by performing search in HALF clock cycle. A 32 × 16-bit proposed macro is designed using 45-nm CMOS technology and post-layout simulations at 1 V supply shows 56% and 63% energy efficiency improvements compared to conventional TCAM and compact TCAM respectively over 25 different search keys despite increasing evaluation speed by 50% with an area overhead of 1 transistor/cell over compact TCAM. 
Entered by:
Sandeep Mishra on 2020-08-05 
 
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